Charge pump apparatus

ABSTRACT

The invention provides a charge pump apparatus including a clock signal generator, a clock freezing circuit, a charge pump circuit, and a feedback circuit. The clock signal generator generates a clock signal. The clock freezing circuit directly receives the clock signal and an enable signal. The clock freezing circuit decides whether to pass or latch a voltage level of the clock signal according to the enable signal to generate a controlled clock signal. The charge pump circuit directly receives the controlled clock signal and operates a charge pump operation on an input voltage to generate a pumping voltage.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefits of U.S. provisionalapplication Ser. No. 62/021,216, filed on Jul. 7, 2014. The entirety ofthe above-mentioned patent application is hereby incorporated byreference herein and made a part of this specification.

BACKGROUND

1. Field of the Invention

The invention relates to a charge pump apparatus. Particularly, theinvention relates to a charge pump apparatus capable of reducing voltageripple on the pumping voltage generated by the charge pump apparatus.

2. Description of Related Art

A charge pump circuit is used to provide a pumping voltage with highervoltage level based on a reference voltage. The voltage level of thepumping voltage may be several times of a voltage level of the referencevoltage. The charge pump circuit may be applied in a plurality ofelectronic apparatus, such as non-volatility memory, display driver andso on.

In conventional art, if the clock signal is not stopped when the voltagelevel of the pumping voltage reaches a target value, a ripple voltagemay be carried on the pumping voltage. For reducing the harmful effectof the ripple voltage, a decoupling capacitor with larger size isneeded. That is, chip size of the charge pump circuit is increased.

In some conventional art, when the voltage level of the pumping voltagereaches the target value, the clock signal can be stopped through aclock source for generating the clock signal. However, there is a timedelay between a timing point of the pumping voltage reaching the targetvalue and a timing of the clock signal being stopped. That is, someun-necessary pulses on the clock signal may be fed to the charge pumpcircuit, and the ripple voltages are generated accordingly.

SUMMARY OF THE INVENTION

The invention is directed to a charge pump apparatus, which caneffectively reduce a ripple voltage on the pumping voltage generated bythe charge pump apparatus.

The invention provides a charge pump apparatus including a clock signalgenerator, a clock freezing circuit, a charge pump circuit, and afeedback circuit. The clock signal generator generates a clock signal.The clock freezing circuit is coupled to the clock signal generator, anddirectly receives the clock signal and an enable signal. The clockfreezing circuit decides whether to hold a voltage level of the clocksignal on a constant level or not according to the enable signal forgenerating a controlled clock signal. The charge pump circuit is coupledto the clock freezing circuit. The charge pump circuit directly receivesthe controlled clock signal and operates a charge pump operation on aninput voltage to generate a pumping voltage.

According to an embodiment of present application, wherein the feedbackcircuit generates the enable signal with a first logic level when thepumping voltage is lower than the preset target voltage, and thefeedback circuit generates the enable signal with a second logic levelwhen the pumping voltage is higher than the preset target voltage.Wherein, the first logic level and the second logic level arecomplementary.

According to an embodiment of present application, wherein the clockfreezing circuit passes the voltage level of the clock signal togenerate the controlled clock signal when the enable signal is at thefirst logic level.

According to an embodiment of present application, wherein the clockfreezing circuit generates the controlled clock signal by latching theclock signal at a time point for the enable signal transited from thefirst logic level to the second logic level.

According to an embodiment of present application, wherein the chargepump circuit includes at least one capacitor, and the controlled clocksignal is directly connected to the at least one capacitor.

According to the above descriptions, the present application provides aclock freezing circuit for stopping a logic level transition of theclock signal. That is, there is no extra pulses on the clock signal betransported to the charge pump circuit when the pumping voltage equal toa target. Accordingly, the voltage ripple on the pumping voltage fromthe charge pump apparatus can be reduced, and the stress issue of thecharge pump apparatus can be improved.

In order to make the aforementioned and other features and advantages ofthe invention comprehensible, several exemplary embodiments accompaniedwith figures are described in detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention.

FIG. 1 illustrates a charge pump apparatus according to an embodiment ofpresent application.

FIG. 2 illustrates a block diagram of the clock freezing circuitaccording to the embodiment of present application.

FIG. 3A illustrates a circuit diagram of the latch circuit according theembodiment of present application.

FIG. 3B illustrates a circuit diagram of the tri-state inverter TINV inFIG. 3A.

FIG. 4 illustrates a block diagram of the feedback circuit according tothe embodiment of present application.

FIG. 5 illustrates a block diagram of the charge pump circuit accordingto the embodiment of present application.

FIG. 6 illustrates a block diagram of the clock generator according tothe embodiment of present application.

DETAILED DESCRIPTION OF DISCLOSED EMBODIMENTS

Referring to FIG. 1, FIG. 1 illustrates a charge pump apparatusaccording to an embodiment of present application. The charge pumpapparatus 100 includes a clock signal generator 110, a clock freezingcircuit 120, a charge pump circuit 130, and a feedback circuit 140. Theclock signal generator 110 is used to generate a clock signal CLK, andthe clock signal CLK is provided to the clock freezing circuit 120. Theclock freezing circuit 120 receives the clock signal CLK and an enablesignal EN, and the clock freezing circuit 120 may decide whether tofreeze the clock signal CLK to generate a controlled clock signal CCLKor not according to the enable signal.

The enable signal EN is generated by the feedback circuit 140. Thefeedback circuit 140 is coupled between the charge pump circuit 130, theclock freezing circuit 120, and the clock signal generator 110. Thefeedback circuit 140 compares a regulated pumping voltage VOUT which isgenerated by the charge pump circuit 130 with a preset target voltage togenerate the enable signal EN. Wherein, the pumping voltage VOUT isgenerated by the charge pump circuit 130 through a charge pump operationbased on the controlled clock signal CCLK. That is, when a voltage levelof the pumping voltage VOUT is lower than the preset target voltage, thefeedback circuit 140 may generate the enable signal EN with a firstlogic level (such as logic level “1”). On the contrary, when the voltagelevel of the pumping voltage VOUT is not lower than the preset targetvoltage, the feedback circuit 140 may generate the enable signal EN witha second logic level (such as logic level “0”). The first and secondlogic levels are complementary. It can be easily seen, when the logiclevel of the enable signal EN is the second logic level, the charge pumpoperation of the charge pump circuit 130 has been competed and no morepulses on the controlled clock signal CCLK is needed.

When the clock freezing circuit 120 receives the enable signal EN withthe second logic level, the clock freezing circuit 120 may freeze theclock signal CLK by holding a voltage level of the clock signal CLK on aconstant level, and generates the controlled clock signal CCLK. Indetail, the clock freezing circuit 120 may immediately hold the voltagelevel of the clock signal CLK on a constant level when the logic levelof the enable signal EN transited from the first logic level to thesecond logic level. That is, when at a timing point T1 which the logiclevel of the enable signal EN transited from the first logic level tothe second logic level, the clock freezing circuit 120 sets the voltagelevel of the clock signal CLK held on the voltage level at the timingpoint T1 to generate the controlled clock signal CCLK. Accordingly, nomore pulses on the controlled clock signal CCLK transported to thecharge pump circuit 130 when the pumping voltage VOUT is higher than thepreset target voltage.

On the other hand, clock freezing circuit 120 may hold the voltage levelof the clock signal CLK by latching the clock signal CLK according tothe enable signal EN.

It should be noted here, when the logic level of the enable signal EN isat the first logic level, the clock freezing circuit 120 may pass theclock signal CLK to be the controlled clock signal CCLK, and the chargepump circuit 130 may operate the charge pump operation based on theclock signal CLK normally.

Besides, the controlled clock signal CCLK is directly connected to thecharge pump circuit 130. When the enable signal EN transited to thesecond logic level, the controlled clock signal CCLK may be held on aconstant voltage level immediately, and no more extra pulses transportedto the charge pump circuit 130.

Referring to FIG. 2, FIG. 2 illustrates a block diagram of the clockfreezing circuit according to the embodiment of present application. Theclock freezing circuit 120 includes a latch circuit 121. An input end ofthe latch circuit 121 receives the clock signal CLK, and an output endthe latch circuit 121 outputs the controlled clock signal CCLK.Moreover, the latch circuit 121 decides whether to hold the voltagelevel of the clock signal CLK or not to generate the controlled clocksignal CCLK according to the enable signal EN.

In some embodiment, the clock signal CLK may include a plurality ofsub-clock signals, such as a first, second, third, and fourth sub-clocksignals, and the phases of the first, second, third, and fourthsub-clock signals are different. Correspondingly, the latch circuit 121may includes four sub-latches respect to the first, second, third, andfourth sub-clock signals for latching the four clock signal to generatefour sub-controlled clock signal, respectively.

Referring to FIG. 3A, FIG. 3A illustrates a circuit diagram of the latchcircuit according the embodiment of present application. The latchcircuit 310 includes inverters INV1 and INV2, switch SW1, and tri-stateinverter TINV. The inverter INV1 receives the clock signal CLK andgenerates an inverted clock signal. The switch SW1 receives the invertedclock signal, and decides whether to transport the inverted clock signalto the inverter INV2 or not according to the enable signal. In FIG. 3A,the switch SW1 is a transmission gate TG1. The transmission gate TG1 iscontrolled by the enable signal EN and an inverted enable signal ENB,and when the enable signal EN is at logic level 1, the transmission gateTG1 is turned on for transporting the inverted clock signal to theinverter INV2. On the contrary, when the enable signal EN is at logiclevel 0, the transmission gate TG1 is cut off, and the inverted clocksignal is not transported to the inverter INV2.

An input end of the inverter INV2 is coupled to an output end of thetri-state inverter TINV, and an output end of the inverter INV2 iscoupled to an input end of the tri-state inverter TINV. Further, thetri-state inverter TINV is controlled by the enable signal EN. When theswitch SW1 is turned off at timing point T1 by the enable signal EN, thetri-state inverter TINV is enabled, and the inverter INV2 and thetri-state inverter form a latch loop for latching the voltage level atthe timing point T1 of the clock signal CLK to be the controlled clocksignal CCLK. On the contrary, when the switch SW1 is turned on by theenable signal EN, the tri-state inverter TINV is disabled, and the clocksignal CLK passes through the inverters INV1 and INV2 to be thecontrolled clock signal CCLK.

Here, the latch circuit can be formed by other logic gates (such as NORgates or NAND gates). The latch circuit in FIG. 3A is only an example,and not use to limit the scope of present application.

Please refer to FIG. 3B, FIG. 3B illustrates a circuit diagram of thetri-state inverter TINV in FIG. 3A. The tri-state inverter TINV includestransistors M1-M4. The transitory M1 and M2 are P-type transistors, andthe transistors M1-M2 are coupled in series between a voltage sourceVDD2 and an output end OUT of the tri-state inverter TINV. Thetransistors M3 and M4 are N-type transistors, and the transistors M3-M4are coupled in series between the output end OUT and a reference groundGND. A gate end of the transistor M1 receives the enable signal EN, agate of the transistor M4 receives the inverted enable signal ENB, andgates of the transistors M2-M3 are coupled to an input end IN of thetri-state inverter TINV. When the transistors M1 and M4 are turned offaccording to the enable signal EN and the inverted enable signal ENBrespectively, the output end OUT of the tri-state inverter TINV is inhigh impedance. On the contrary, when the transistors M1 and M4 areturned on according to the enable signal EN and the inverted enablesignal ENB respectively, the logic levels of the output end OUT and theinput end IN are complementary.

Referring to FIG. 4, FIG. 4 illustrates a block diagram of the feedbackcircuit according to the embodiment of present application. The feedbackcircuit 140 includes a voltage regulator 441 and a comparator 442. Thevoltage regulator 441 receives the pumping voltage VOUT, and generates acompared voltage COMPV by regulating the pumping voltage VOUT. Thecomparator 442 receives the compared voltage COMPV and the preset targetvoltage VREF, and generates the enable signal EN by comparing thecompared voltage COMPV and the preset target voltage VREF.

Referring to FIG. 5, FIG. 5 illustrates a block diagram of the chargepump circuit according to the embodiment of present application. Thecharge pump circuit 130 includes a switching circuit 131 and at leastone capacitor C1-CM. The charge pump circuit 130 may receive a voltagesource VDD2 and the controlled clock signals CCLK1-CCLKM provided to oneor more of the capacitors C1-CM in a specified sequence by the switchingcircuit 131 to generate a higher pumping voltage VOUT. The voltagesource VDD2 may be the operation voltage of the switching circuit 131.It should be noted here, the controlled clock signals CCLK1-CCLKM areprovided to the charge pump circuit 130 for the charge pump operation,and the controlled clock signals CCLK1-CCLKM are respectively directlyprovided to the capacitors C1-CM. That is, when voltage levels of thecontrolled clock signals CCLK1-CCLKM are held on constant voltagelevels, the charge pump operation can be stopped as soon as possible.

Referring to FIG. 6, FIG. 6 illustrates a block diagram of the clockgenerator according to the embodiment of present application. The clockgenerator 110 is a ring oscillator, and includes a plurality ofinverters IV1-IVN and a nand gate NAND1. A first input end of the nandgate NAND1 receives an enable signal EN. The inverters IV1-IVN arecoupled in series between a second input end and an output end of thenand gate NAND1, and the output end of the serial inverters IV1-IVNoutputs the clock signal CLK. A frequency of the clock signal CLK may becontrolled by a number of the inverters IV1-IVN and gate delays of eachof the inverters IV1-IVN and the nand gate NAND1. Of course, the ringoscillator in FIG. 6 is only an example, and any other clock generatorknow by persons skilled in the art can be applied in the presentapplication.

The enable signal EN can be used to enable or disable the clockgenerator 110. In this embodiment, when the enable signal EN is logichigh, the clock generator 110 can be enabled, and the clock signal CLKcan be generated. On the contrary, when the enable signal EN is logiclow, the clock generator 110 can be disabled, and a transition of theclock signal CLK is stopped.

In summary, the present application provides a clock freezing circuit tohold the voltage level of the clock signal when the pumping voltagereaches the target value. That is, no more extra pulses be transportedto the charge pump circuit, and the ripple voltage on the pumpingvoltage can be reduced. The stress issue and the area penalty of thecharge pump apparatus can be improved.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of theinvention without departing from the scope or spirit of the invention.In view of the foregoing, it is intended that the invention covermodifications and variations of this invention provided they fall withinthe scope of the following claims and their equivalents.

What is claimed is:
 1. A charge pump apparatus, comprising: a clocksignal generator, generating a clock signal; a clock freezing circuit,coupled to the clock signal generator, directly receiving the clocksignal and an enable signal, and deciding whether to pass a voltagelevel of the clock signal or not according to the enable signal forgenerating a controlled clock signal; a charge pump circuit, coupled tothe clock freezing circuit, directly receiving the controlled clocksignal and operating a charge pump operation on an input voltage togenerate a pumping voltage; and a feedback circuit, coupled to thecharge pump circuit and the clock freezing circuit, wherein the feedbackcircuit compares the pumping voltage and a preset target voltage togenerate the enable signal.
 2. The charge pump apparatus as claimed inclaim 1, wherein the feedback circuit generates the enable signal with afirst logic level when the pumping voltage is lower than the presettarget voltage, and the feedback circuit generates the enable signalwith a second logic level when the pumping voltage is higher than thepreset target voltage, wherein the first logic level and the secondlogic level are complementary.
 3. The charge pump apparatus as claimedin claim 2, wherein the clock freezing circuit passes the voltage levelof the clock signal to generate the controlled clock signal when theenable signal is at the first logic level.
 4. The charge pump apparatusas claimed in claim 3, wherein the clock freezing circuit generates thecontrolled clock signal by latching the clock signal at a time point forthe enable signal transited from the first logic level to the secondlogic level.
 5. The charge pump apparatus as claimed in claim 4, whereinthe clock freezing circuit comprises: a latch circuit, receives theclock signal and the enable signal, and decide whether to latch theclock signal or not to generated the controlled clock signal accordingto the enable signal.
 6. The charge pump apparatus as claimed in claim5, wherein the latch circuit comprises: a first inverter, receives theclock signal and generates an inverted clock signal; a switch, has afirst end for receiving the inverted clock signal, and controlled by theenable signal to be turned on or turned off; a second inverter, has ainput end coupled to a second end of the switch, and an output end ofthe second inverter generates the controlled clock signal; and atri-state inverter, has an input end, an output end and a control end,wherein the output end of the tri-state inverter is coupled to thesecond end of the switch, the input end of the tri-state inverter iscoupled to the output end of the second inverter, and the control end ofthe tri-state inverter receives the enable signal.
 7. The charge pumpapparatus as claimed in claim 5, wherein the switch is a transmissiongate, and a first end of the transmission gate receives the invertedclock signal, a second end of the transmission gate is coupled to theinput end of the second inverter, and a first and second control ends ofthe transmission gate respectively receive the enable signal and ainverted enable signal.
 8. The charge pump apparatus as claimed in claim1, wherein the feedback circuit comprises: a voltage regulator, receivesthe pumping voltage and generated a compared voltage according to thepumping voltage; and a comparator, coupled to the voltage regulator andthe clock freezing circuit, and the comparator compares the comparedvoltage and the preset target voltage to generate the enable signal. 9.The charge pump apparatus as claimed in claim 1, wherein the clocksignal generator further receives the enable signal, and the clocksignal generator decides whether to generate the clock signal or notaccording to the enable signal.
 10. The charge pump apparatus as claimedin claim 1, wherein the charge pump circuit comprises at least onecapacitor, and the controlled clock signal is directly connected to theat least one capacitor.
 11. The charge pump apparatus as claimed inclaim 1, wherein the clock signal comprises a first, second, third andfourth sub-clock signals, and the phases of the first, second, third andfourth sub-clock signals are different.
 12. The charge pump apparatus asclaimed in claim 1, wherein the clock signal generator is a ringoscillator.